| 0–4 |
Reveal substrate, source, drain, dielectric and gate |
Establish components before they move |
| 4–10 |
Gate charge and field appear; holes recede; electrons gather |
Gate control changes carrier distribution |
| Around 10 |
Channel continuity receives a visual/sound accent |
The illustrated threshold crossing |
| 11.5–17 |
Electron drift and a separate current arrow |
Distinguish vertical gate control and lateral transport |
| 17–22 |
Charge layers and capacitor labels emerge from the structure |
Link the device to the capacitance picture |
| 22–28 |
Extrusion, rotation and widening perspective |
Preserve the object as the view becomes spatial |
| 28–34 |
Electrolyte replaces the dielectric illustration |
Introduce ions without implying a literal fabrication step |
| 34–44 |
Anions gather near the gate, cations near the semiconductor; electrons accumulate across the interface |
Interfacial redistribution and near-neutral bulk |
| 44–50 |
Camera dives; macro and magnified representations overlap briefly |
Change scale without losing the interface |
| 50–60 |
Charge layers, effective distance and field cues remain visible |
Inspect why interfacial capacitance can be large |
| 60–66 |
Pull out and introduce the conventional reference |
Prepare a common comparison |
| 66–78 |
Both channels follow the same charge parameter; voltage columns differ |
Compare common target charge, not common voltage |
| 78–88 |
Increase solid-dielectric stress; show defects and a path |
Illustrate a possible gate-related failure |
| 88–96.4 |
Limitations remain on screen as the camera relaxes |
Prevent an absolute reliability claim |
| 96.4–102 |
Flatten the device and present the causal chain |
Close in the original visual language |